Method of generating RC technology file

ABSTRACT

A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

BACKGROUND

As semiconductor technologies evolve, integrated circuits (IC) havemigrated to small feature sizes, such as 65 nanometers, 45 nanometers,32 nanometers and below. Semiconductor technologies with small featuresizes lead to more interactions between semiconductor fabrication anddesign. For example, the impact of parasitic effects will become moreimportant for devices with small feature sizes. A variety of simulationand optimization procedures may be performed by IC designers to ensurethe devices with small feature sizes meet the performance index to whichthey are specified.

One parasitic effect is parasitic elements derived from electricalcharacteristics of interconnected conductors of an IC. As known in theart, in a front-end-of-line (FEOL) process, an active layer is formed ina substrate. Once the active layer has been created, in aback-end-of-line (BEOL) process, a plurality of interconnect layers areformed on top of the active layer. In each interconnect layer, a metallayer is deposited first, then patterned so that various metalconductors are created. The metal conductors in different layers areinterconnected by vias. As metal conductors are located in closeproximity to each other, parasitic capacitances are formed between anytwo of them. In addition, a parasitic capacitance is also formed betweena metal interconnect and ground.

In order to design high performance integrated circuits, the parasiticcapacitance, inductance and resistance of interconnect conductors may bemodeled so that some critical issues such as timing, noise andreliability can be accurately assessed. Various Electronic DesignAutomation (EDA) tools may be used to extract parasitic capacitance andresistance. For example, an EDA tool such as RAPHAEL from SYNOPSYS mayfirst receive a SPICE model file from an IC foundry. Then, the EDA toolcalculates the parasitic capacitance values related to each interconnectconductor by means of a field solver. The outcome of the field solver issaved as a resistance-capacitance (RC) technology file.

The generation of RC technology files is timing consuming. In addition,for an IC foundry, different clients may have slightly differentinterconnect structures. However, an IC foundry is required to dedicateone RC technology file for each interconnect structure despite that thedifference between a variety of interconnect structures are minimal. Inconsideration of the large number of clients an IC foundry may have, thegeneration of RC technology files in a limited period of time is achallengeable job.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a flowchart including a sequence of steps forgenerating resistance-capacitance (RC) technology files;

FIG. 2 depicts in a more detailed flowchart a sequence of steps forgenerating RC technology files;

FIG. 3 illustrates three modular RC structures upon which three macromodels are based;

FIG. 4 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprisingthick interconnect conductors;

FIG. 5 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in an modular RC structure comprisingthin interconnect conductors;

FIG. 6 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprising boththick and thin interconnect conductors;

FIG. 7 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprisingdielectric thickness variations;

FIG. 8 illustrates an example of deriving a metal scheme's parasiticcapacitance from two macro models; and

FIG. 9 illustrates a simplified block diagram of an embodiment computersystem that can be used to implement the method of generating RCtechnology files in accordance with an embodiment.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the variousembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, methods of generating a variety ofresistance-capacitance (RC) technology files based on a macro RC model.The invention may also be applied, however, to generating RC technologyfiles based upon a variety of macro RC models.

FIG. 1 illustrates a flowchart including a sequence of steps forgenerating RC technology files. In step 100, a plurality of schematicvariation profiles are provided by an integrated circuit (IC) foundry.It should be noted that while FIG. 1 illustrates three schematicvariation profiles, the number of schematic variation profilesillustrated herein is limited solely for the purpose of clearlyillustrating the inventive aspects of the various embodiments. Thepresent invention is not limited to any specific number of schematicvariation profiles. Each schematic variation profile may includefabrication process parameters of the various interconnect layers in anIC, such as the numbers of interconnect layers, the spacing, width,resistivity and thickness of those interconnect layers as specified inthe design rules, the dielectric constant, thickness, stacking ofdielectric layers and the like.

In step 110, modular RC structures are generated based upon theplurality of schematic variation profiles. In accordance with anembodiment, the IC foundry inputs the schematic variation profileswherein a variety of schematic variation profiles may have the sameinterconnect conductors. More particularly, the thickness, width andspacing of the interconnect conductors of those schematic variationfiles are same. The only difference is that each schematic variationprofile may have a different number of dielectric layers. In addition,the thickness and dielectric constant of dielectric layers may bedifferent too. Because the plurality of schematic variation profiles aresimilar except the differences described above, one or more schematicvariation profiles may be selected to represent the plurality ofschematic variation profiles. The selected schematic variation profilesare directed to an Electronic Design Automation (EDA) tool as modular RCstructures.

In step 120, a field solver (not shown but illustrated in FIG. 2) of theEDA tool receives the modular RC structures. The field solver is aspecialized software program capable of solving Maxwell's equations.Based upon the information from the modular RC structures, the fieldsolver can identify a variety of primitives of conductive features andthen calculate the parasitic capacitance of each primitive. Theextracted capacitances from the primitives form a RC model.

In step 130, the RC model extracted from step 120 is defined as a macroRC model for the plurality of schematic variation profiles. In otherwords, a macro RC model is retrieved from a group of schematic variationprofiles having similar interconnect conductors while the dielectriclayers may have different characteristics. The macro RC model isre-usable and can be used as a base to generate a RC technology file foreach schematic variation profile in the plurality of schematic variationfiles given by the IC foundry.

In step 140, based upon the macro RC model generated in step 130, a RCtechnology file for each metal scheme can be generated in considerationof the structural difference between each metal scheme and the metalscheme upon which the macro model is based. In other words, a group ofmetal schemes may share a similar interconnect distribution pattern(e.g., metal schemes 800, 810 and 820 shown in FIG. 8), but thedielectric layers of each metal scheme are slightly different from thoseof the metal scheme upon which the macro RC model is based. Thedielectric layers between interconnect conductors of each metal schemecan be replaced by an equivalent dielectric layer. As a result, the RCtechnology file of a metal scheme can be derived from the macro RC modelin consideration of the difference between the equivalent dielectriclayer of the metal scheme and the equivalent dielectric layer of themacro RC model.

As it is known in the art, using an equivalent dielectric layer toreplace a plurality of dielectric layers between two conductors does nothave an impact on the parasitic capacitance between the two conductors.As a result, the group of metal schemes having a similar interconnectdistribution pattern can be simplified to a group of metal schemeshaving the same location of interconnect conductors except differentequivalent dielectric layers. As described in step 130, a metal schemeof this group may be selected as a modular RC structure. A macro RCmodel can be calculated based on the modular RC structure by means of afield solver. The RC technology files of other metal schemes of thisgroup may be derived from the macro RC model based upon a simplemathematical equation rather than complicated Maxwell's equations. Thesimple mathematical equation will be described in detail with respect toFIG. 7.

In step 150, a plurality of RC technology files are generated. Each RCtechnology file may include a table wherein the capacitance between twointerconnect conductors and the capacitance between an interconnectconductor and ground are presented. The validity of each RC technologyfile may be verified through a variety of product assurance processessuch as semiconductor process characterization and failure analyses (notshown but illustrated in FIG. 2). Subsequently, the RC technology filesshown in step 150 will be provided to various IC design customers. Inorder to describe the embodiments and the advantages more fully, FIG. 2depicts in a more detailed flowchart a sequence of steps for generatingRC technology files. The step 140 in FIG. 2 includes a process ofreplacing various dielectric layers with an equivalent dielectric layerin a modular RC structure comprising dielectric thickness variations.The step 140 will be described in detail with respect to FIG. 7.

FIG. 3 illustrates three modular RC structures upon which three macro RCmodels are based. A modular RC structure 300 includes a substrate, aconductive layer (not shown), a conductive polycrystalline (poly) layer(not shown), a variety of interconnect layers and dielectric materialsformed between any two interconnect layers. As known in the art,interconnect conductors in some upper layers such as the seventhinterconnect layer, the eighth interconnect layer and the ninthinterconnect layer may be thicker than those in some lower layers suchas the sixth interconnect layer and below. As illustrated in FIG. 3, themodular RC structure 300 represents a first group of metal schemeswherein each metal scheme may have the same interconnect conductors inthe upper layers comprising thicker conductors. However, each metalscheme in this group may have different dielectric layers. Moreparticularly, each metal scheme may have a different number ofdielectric layers and each dielectric layer may have different processcharacteristics (e.g., thickness and dielectric constant value).Nevertheless, the dielectric layers in each metal scheme may be replacedby an equivalent dielectric layer. The process of replacing variousdielectric layers with an equivalent dielectric layer will be describedin detail with respect to FIG. 3.

Similarly, a modular RC structure 310 and a modular RC structure 320include a substrate, a conductive layer (not shown), a conductive polylayer (not shown), a variety of interconnect layers and dielectricmaterials formed between any two interconnect layers. The interconnectconductors in the modular RC structure 310 are located in the lowerlayers. As described above, the interconnect conductors in lower layersare thinner than their counterparts in upper layers. The modular RCstructure 320 provides another alternative metal scheme wherein theinterconnect conductors comprise both thick metal conductors and thinmetal conductors. In other words, the interconnect conductors in themodular RC structure 320 are located in both upper layers and lowerlayers.

FIG. 4 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprisingthick interconnect conductors. In the modular RC structure 300, theinterconnect conductors are located in the seventh interconnect layer,the eighth interconnect layer and the ninth interconnect layer. As shownin FIG. 4, the dielectric layers underneath the seventh interconnectlayer do not comprise interconnect conductors. The electrical fieldbetween two interconnect conductors in the upper layers stores energy sothat a capacitance is formed between two interconnect conductors. Asknown in the art, the magnitude of the electrical field decreases as thedistance from a location to the source increases. As shown in FIG. 4,the dielectric layers underneath the seventh interconnect layer arelocated relatively far away from the interconnect layers, and thereforemay have minimal impact on the capacitance between two interconnectconductors located in the upper layers. As a result, the dielectriclayers can be simplified into a single equivalent dielectric layer asshown in a modular RC structure 400. As known in the art, eachdielectric layer comprises two electrical characteristics, namely thethickness of a dielectric layer and the permittivity of a dielectriclayer. The equivalent dielectric constant of N dielectric layers can becalculated as follows:

$ɛ_{eff} = {\left( {\sum\limits_{n = 1}^{N}\frac{t_{n}}{ɛ_{n}}} \right)^{- 1} \cdot \left( {\sum\limits_{n = 1}^{N}t_{n}} \right)}$where t_(n) is the thickness of the nth dielectric layer and ∈_(n) isthe permittivity of the nth dielectric layer. The equivalent thicknesscan be calculated as follows:

$t_{eff} = \left( {\sum\limits_{n = 1}^{N}t_{n}} \right)$One advantageous feature of the equivalent dielectric layer is that thedifference between two metal schemes having a similar interconnectdistribution pattern, but different dielectric layers may be simplifiedinto the difference between two equivalent dielectric layers. Moreparticularly, a variety of electrical characteristics from variousdielectric layers can be replaced with two equivalent characteristics asshown above.

FIG. 5 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprising thininterconnect conductors. As shown in FIG. 5, the interconnect conductorsare located in the fourth interconnect layer, the fifth interconnectlayer and the sixth interconnect layer. The dielectric layers above thesixth interconnect layer do not comprise interconnect conductors.Therefore, the dielectric layers can be simplified into a singleequivalent dielectric layer as shown in a modular RC structure 500. Theequations for the equivalent thickness and the equivalent dielectricconstant are the same as those described above with respect to FIG. 4.

FIG. 6 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprising boththick and thin interconnect conductors. As shown in FIG. 6, theinterconnect conductors are located in the fourth interconnect layer,the seventh interconnect layer and the eighth interconnect layer. Thedielectric layers between the fourth interconnect layer and the seventhinterconnect layer do not comprise interconnect conductors. Therefore,the dielectric layers can be simplified into a single equivalentdielectric layer as shown in a modular RC structure 600. Similarly, theequations for the equivalent thickness and the equivalent dielectricconstant are the same as those described above with respect to FIG. 4.It should be noted that while the upper layers in FIG. 6 comprise thickinterconnect conductors, a person having ordinary skill in the art willrecognize that upper layers comprising thin interconnect conductors arewithin the scope of the present invention.

FIG. 7 illustrates a process of replacing various dielectric layers withan equivalent dielectric layer in a modular RC structure comprisingdielectric thickness variations. A dielectric layer is made of siliconoxide, silicon nitride and the like. Due to the difficulties ofproducing a thin layer across the entire wafer during chip fabricationprocess, small dielectric layer thickness variations may exist incomparison of the thickness defined during a back-end-of-line (BEOL)stage. The dielectric layer thickness variations may cause parasiticcapacitance variations, which may exceed the specification defined basedon the BEOL thickness. As shown in FIG. 7, dielectric thicknessvariations can be fully considered through the process of replacingvarious dielectric layers with an equivalent dielectric layer. A modularRC structure 700 depicts the BEOL thickness of the dielectric layersbetween the fourth metal layer and the seventh metal layer. During chipfabrication process, the real thickness of each dielectric layer maydiffer from the nominal BEOL thickness. A modular RC structure 710 showsthe variations. A wafer inspection system may detect the variation ofeach dielectric layer. The detected thickness of each dielectric layeris used to calculate the equivalent dielectric constant and equivalentthickness. A modular RC structure 720 illustrates an equivalentdielectric layer comprising each dielectric layer's thickness variation.As a result, the modular RC structure 720 reflects the real thickness ofeach dielectric layer rather than the projected thickness defined duringthe BEOL stage.

FIG. 8 illustrates an example of deriving a metal scheme's parasiticcapacitances from two macro models. FIG. 8 illustrates three metalschemes comprising both thick and thin interconnects. In accordance withan embodiment, a metal scheme 800 and a metal scheme 820 are selected asmodular RC structures. A field solver receives the interconnect files ofboth the metal scheme 800 and the metal scheme 820 and calculates theparasitic capacitance values. The outcome of the field solver is the RCtechnology files for the metal scheme 800 and the metal scheme 820. TheRC technology file of the modular RC structure 810 can be derived fromthe RC technology files of modular RC structures 800 and 820.

For a modular RC structure having n conductors and one ground, there are(n+1)n/2 coupling capacitances and n parasitic capacitances from nconductors to ground. As described above, the capacitances of themodular RC structures 800 and 820 have been calculated by a field solverthrough solving Maxwell's equations. The capacitances of the metalscheme 810 can be calculated by the following equations:C _(m) =C _(i1) +S×fwhere C_(m) is the capacitances in the metal scheme 810 (e.g., thecapacitances between the conductor M_IV_A and M_II_A in modular RCstructure 810), C_(i1) is the corresponding capacitance in the modularRC structure 800 (e.g., the capacitances between the conductor M_III_Aand M_II_A in modular RC structure 800). S and f are defined as follows:

$S = \frac{C_{i\; 2} - C_{i\; 1}}{t_{i\; 2} - t_{i\; 1}}$$f = \frac{\left( {t_{m} - t_{i\; 1}} \right) \times ɛ_{m}}{ɛ_{i\; 1} + {\left( {ɛ_{i\; 2} - ɛ_{i\; 1}} \right) \times \left( \frac{t_{m} - t_{i\; 1}}{t_{i\; 2} - t_{i\; 1}} \right)}}$From the equations above, the capacitances of the metal scheme 810 canbe calculated by the following equation:

$C_{m} = {C_{i\; 1} + C_{i\; 2} - {C_{i\; 1} \times \frac{\left( {t_{m} - t_{i\; 1}} \right)}{t_{i\; 2} - t_{i\; 1}} \times \frac{ɛ_{m}}{ɛ_{i\; 1} + {\left( {ɛ_{i\; 2} - ɛ_{i\; 1}} \right) \times \left( \frac{t_{m} - t_{i\; 1}}{t_{i\; 2} - t_{i\; 1}} \right)}}}}$One advantageous feature of calculating a metal scheme's capacitancesbased on two modular RC structures is that the calculation resources canbe reduced because the equation above only comprises a simplemathematical equation rather complicated Maxwell's equations. It shouldbe noted that in a semiconductor foundry, there are a variety of modularRC structures having a similar interconnect distribution pattern butdifferent dielectric layers. By simplifying various dielectric layersinto a single equivalent dielectric layer and further selecting twomodular RC structures as macro RC models, the other metal schemes'capacitances can be calculated by a simple mathematical equation shownabove.

FIG. 9 illustrates a simplified block diagram of a computer system 900that can be used to implement the method of generating RC technologyfiles in accordance with an embodiment. The computer system 900 includesan RC technology file generator 910, a memory 920, a processor 930, astorage unit 940, user interface input devices 950, user interfaceoutput devices 960 and a data bus 970. It should be noted that thisdiagram is merely an example of a general purpose computer, which shouldnot unduly limit the scope of the claims. Many other configurations of acomputer are within the scope of this disclosure. One of ordinary skillin the art would also recognize the aging simulation method may beperformed by other computer systems including a portable computer, aworkstation, a network computer, or the like.

The RC technology file generator 910 may be a physical device, asoftware program, or a combination of software and hardware such asApplication Specific Integrated Circuits (ASIC). In accordance with anembodiment, when a user launches the RC technology generation methodthrough the user interface input devices 950, the processor 930 loadsthe schematic variation profiles and other relevant information from thestorage unit 940. According to an embodiment, the RC technologygeneration method is implemented as a software program, the process 930loads the software program from the RC technology file generator 910 andoperates it in the memory 920. After the processor 930 performs eachstep of FIG. 1, the processor 930 sends the RC technology files for eachschematic variation profile to the user interface output devices 960. Inaccordance with the RC technology profile of each schematic variationprofile, design corners such as timing, noise and reliability can beestimated.

Although embodiments of the present invention and its advantages havebeen described in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. A method comprising: identifying a modular resistance-capacitance (RC) structure from a plurality of metal schemes wherein the modular RC structure has an interconnect configuration similar to interconnect configurations of the plurality of metal schemes; calculating, using a processor, one or more capacitance values of the modular RC structure by using a field solver; calculating, using a processor, a first equivalent dielectric constant and a first equivalent height of the modular RC structure based upon a variety of interconnect layers not having interconnects; calculating, using a processor, a second equivalent dielectric constant and a second equivalent height for each of the plurality of metal schemes; determining, using a processor, differences between the first and second equivalent dielectric constants and the first and second equivalent heights; deriving, using a processor, capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure and from the differences between the first and second equivalent dielectric constants and the first and second equivalent heights; and storing the derived capacitance values in a computer-readable memory.
 2. The method of claim 1, further comprising: receiving a plurality of schematic variation profiles from an IC foundry; and dividing the plurality of schematic variation profiles into one or more groups of metal schemes.
 3. The method of claim 1, wherein a plurality of interconnects are located in upper thick metal layers of the modular RC structure and the variety of interconnect layers not having interconnects are located in lower thin metal layers.
 4. The method of claim 1, wherein a plurality of interconnects are located in lower thin metal layers of the modular RC structure and the variety of interconnect layers not having interconnects are located in upper thick metal layers.
 5. The method of claim 1, wherein a plurality of interconnects are located in both upper thick metal layers and lower thin metal layers of the modular RC structure and the variety of interconnect layers not having interconnects are located in between the upper thick metal layers having interconnects and the lower thin metal layers having interconnects.
 6. The method of claim 1, wherein a plurality of interconnects are located in both upper thin metal layers and lower thin metal layers of the modular RC structure and the variety of interconnect layers not having interconnects are located in between the upper thin metal layers having interconnects and the lower thin metal layers having interconnects.
 7. The method of claim 1, wherein the field solver has a three-dimensional accuracy.
 8. The method of claim 1, further comprising: generating a RC technology file based upon the capacitance values of the modular RC structure; and generating a plurality of RC technology files based upon the capacitance values of each of the plurality of metal schemes.
 9. A method comprising: identifying a first modular resistance-capacitance (RC) structure from a plurality of metal schemes wherein the first modular RC structure has an interconnect configuration similar to interconnect configurations of the plurality of metal schemes; identifying a second modular RC structure from the plurality of metal schemes; calculating, using a processor, one or more capacitance values of the first modular RC structure by using a field solver; calculating, using a processor, one or more capacitance values of the second modular RC structure by using the field solver; calculating, using a processor, an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; deriving, using a processor, capacitance values of each of the plurality of metal schemes from the capacitance values of the first and the second modular RC structures and from the equivalent dielectric constant and the equivalent height of each of the plurality of metal schemes; and storing the derived capacitance values in a computer-readable memory.
 10. The method of claim 9, further comprising: identifying at least one more modular RC structure; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the first, the second and the one more modular RC structures.
 11. The method of claim 9, further comprising finding a group of metal schemes having a plurality of interconnects located in upper thick metal layers of the group of metal schemes and a variety of interconnect layers not having interconnects located in lower thin metal layers.
 12. The method of claim 9, further comprising finding a group of metal schemes having a plurality of interconnects located in lower thin metal layers of the group of metal schemes and a variety of interconnect layers not having interconnects located in upper thick metal layers.
 13. The method of claim 9, further comprising finding a group of metal schemes having a plurality of interconnects located in both upper thick metal layers and lower thin metal layers of the group of metal schemes and a variety of interconnect layers not having interconnects are located in between the upper thick metal layers having interconnects and the lower thin metal layers having interconnects.
 14. The method of claim 9, further comprising finding a group of metal schemes having a plurality of interconnects located in both upper thin metal layers and lower thin metal layers of the group of metal schemes and a variety of interconnect layers not having interconnects are located in between the upper thin metal layers having interconnects and the lower thin metal layers having interconnects.
 15. The method of claim 9, further comprising: detecting dielectric layer thickness variations of a metal scheme; calculating an equivalent height and equivalent dielectric constant in consideration of the dielectric layer thickness variations; and deriving capacitance values of the metal scheme from the capacitance values of the first and the second modular RC structures.
 16. The method of claim 9, further comprising: receiving a plurality of schematic variation profiles; generating a plurality of modular RC structures; calculating capacitance values for each of the modular RC structures; finding a macro RC model for the schematic variation profiles; and deriving a RC technology file for each schematic variation profile from the macro RC model.
 17. A computer program product having a non-transitory computer-readable medium with a computer program embodied thereon, the computer program comprising: computer program code for identifying a first modular RC structure from a plurality of metal schemes wherein the first modular RC structure has an interconnect configuration similar to interconnect configurations of the plurality of metal schemes; computer program code for calculating one or more capacitance values of the first modular RC structure by using a field solver; computer program code for calculating a first equivalent dielectric constant and a first equivalent height of the first modular RC structure based upon a variety of interconnect layers not having interconnects; computer program code for calculating a second equivalent dielectric constant and a second equivalent height for each of the plurality of metal schemes; computer program code for determining differences between the first and second equivalent dielectric constants and the first and second equivalent heights; and computer program code for deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the first modular RC structure and from the differences between the first and second equivalent dielectric constants and the first and second equivalent heights.
 18. The computer program product of claim 17, further comprising: computer program code for identifying a second modular RC structure from the plurality of metal schemes; computer program code for calculating one or more capacitance values of the second modular RC structure by using the field solver; computer program code for calculating an equivalent dielectric constant and an equivalent height for the second modular RC structure; and computer program code for deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the first and the second modular RC structures.
 19. The computer program product of claim 18, further comprising: computer program code for detecting dielectric layer thickness variations of a metal scheme; computer program code for calculating an equivalent height and equivalent dielectric constant in consideration of the dielectric layer thickness variations; and computer program code for deriving capacitance values of the metal scheme from the capacitance values of the first and the second modular RC structures.
 20. The computer program product of claim 17, further comprising: computer program code for receiving a plurality of schematic variation profiles from an IC foundry; and computer program code for dividing the plurality of schematic variation profiles into one or more groups of metal schemes.
 21. The computer program product of claim 17, further comprising: computer program code for generating a RC technology file based upon the capacitance values of the first modular RC structure; and computer program code for generating a plurality of RC technology files based upon the capacitance values of each of the plurality of metal schemes.
 22. The computer program product of claim 17, further comprising: computer program code for finding a group of metal schemes having a plurality of interconnects located in upper thick metal layers of the metal schemes and a variety of interconnect layers not having interconnects located in lower thin metal layers; computer program code for finding a group of metal schemes having a plurality of interconnects located in lower thin metal layers of the metal schemes and a variety of interconnect layers not having interconnects located in upper thick metal layers; computer program code for finding a group of metal schemes having a plurality of interconnects located in both upper thick metal layers and lower thin metal layers of the metal schemes and a variety of interconnect layers not having interconnects are located in between the upper thick metal layers having interconnects and the lower thin metal layers having interconnects; and computer program code for finding a group of metal schemes having a plurality of interconnects located in both upper thin metal layers and lower thin metal layers of the metal schemes and a variety of interconnect layers not having interconnects are located in between the upper thin metal layers having interconnects and the lower thin metal layers having interconnects. 